Impact of Irradiation Side on Muon-Induced Single-Event Upsets in 65-nm Bulk SRAMs

被引:0
|
作者
Deng, Yifan [1 ]
Watanabe, Yukinobu [2 ]
Manabe, Seiya [1 ,3 ]
Liao, Wang [4 ]
Hashimoto, Masanori [5 ]
Abe, Shin-Ichiro [6 ]
Tampo, Motonobu [7 ]
Miyake, Yasuhiro [7 ,8 ]
机构
[1] Kyushu Univ, Interdisciplinary Grad Sch Engn Sci, Fukuoka 8168580, Japan
[2] Kyushu Univ, Fac Engn Sci, Fukuoka 8168580, Japan
[3] Natl Inst Adv Ind Sci & Technol, Res Inst Measurement & Analyt Instrumentat RIMA, Tsukuba 3058568, Japan
[4] Kochi Univ Technol, Sch Syst Engn, Kochi 7828502, Japan
[5] Kyoto Univ, Grad Sch Informat, Kyoto 6068501, Japan
[6] Japan Atom Energy Agcy, Res Grp Radiat Transport Anal, Ibaraki 3191184, Japan
[7] High Energy Accelerator Res Org KEK, Muon Sci Lab, Tsukuba 3191106, Japan
[8] Japan Proton Accelerator Res Complex Ctr, Mat & Life Sci Div, Muon Sect, Ibaraki 3191195, Japan
基金
日本学术振兴会;
关键词
Mesons; Radiation effects; Single event upsets; Telescopes; SRAM chips; Particle beams; Monte Carlo methods; Accelerated testing; Geant4; irradiation side; Monte Carlo (MC) simulation; negative and positive muons; single-event upset (SEU); soft error rate (SER); static random-access memories (SRAMs); INDUCED SEU RATES; MODEL;
D O I
10.1109/TNS.2024.3378216
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have newly analyzed negative and positive muon-induced single-event upset (SEU) data in irradiation tests from the package side (PS) of 65-nm bulk static random-access memory (SRAM) and compared with previous results of irradiation tests from the board side (BS). The peak SEU cross section is 28 MeV/c for PS irradiation, which differs from 38 MeV/c for BS irradiation. The magnitude of the peak SEU cross section for PS irradiation is approximately twice that of BS irradiation for both positive and negative muons. Through simulations using Geant4, we explain the difference quantitatively. This simulation also reproduces the experimental SEU cross sections for tilted incidence of the muon beam onto the device board. The soft error rates (SERs) are estimated under a realistic environment considering the zenith angle distribution of muon flux. As a result, it was found that the estimated SERs were not significantly different from the case without zenith angle distribution. This result indicates that experimental data from irradiation tests in which the device board is placed perpendicular to the incident beam are expected to be useful for estimating muon-induced SERs in terrestrial environments.
引用
收藏
页码:912 / 920
页数:9
相关论文
共 50 条
  • [31] Single-Event Upsets in SRAMs With Scaling Technology Nodes Induced by Terrestrial, Nuclear Reactor, and Monoenergetic Neutrons
    Chen, Wei
    Guo, Xiaoqiang
    Wang, Chenhui
    Zhang, Fengqi
    Qi, Chao
    Wang, Xun
    Jin, Xiaoming
    Wei, Yuan
    Yang, Shanchao
    Song, Zhaohui
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2019, 66 (06) : 856 - 865
  • [32] Impacts of Proton Radiation on Heavy-Ion-Induced Single-Event Transients in 65-nm CMOS Technology
    Wu, Zhenyu
    Chen, Shuming
    Chen, Jianjun
    Huang, Pengcheng
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2019, 66 (01) : 177 - 183
  • [33] Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations
    Hubert, Guillaume
    Artola, Laurent
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2013, 60 (06) : 4421 - 4429
  • [34] nMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology
    Wu, Zhenyu
    Chen, Shuming
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2018, 65 (01) : 418 - 425
  • [35] Susceptibility of Planar and 3D Tri-Gate Technologies to Muon-induced Single Event Upsets
    Seifert, Norbert
    Jahinuzzaman, Shah
    Velamala, Jyothi
    Patel, Nikunj
    2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2015,
  • [36] Single-Event Upsets in a 7-nm Bulk FinFET Technology With Analysis of Threshold Voltage Dependence
    D'Amico, Joseph V.
    Ball, Dennis R.
    Cao, Jingchen
    Xu, Lyuan
    Rathore, Mike
    Wen, Shi-Jie
    Fung, Rita
    Narasimham, Balaji
    Kauppila, Jeffrey S.
    Massengill, Lloyd W.
    Bhuva, Bharat L.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2021, 68 (05) : 823 - 829
  • [37] Single event transient pulse width measurement of 65-nm bulk CMOS circuits
    岳素格
    张晓林
    赵馨远
    Journal of Semiconductors, 2015, 36 (11) : 101 - 104
  • [38] Single event transient pulse width measurement of 65-nm bulk CMOS circuits
    岳素格
    张晓林
    赵馨远
    Journal of Semiconductors, 2015, (11) : 101 - 104
  • [39] Single event transient pulse width measurement of 65-nm bulk CMOS circuits
    Yue, Suge
    Zhang, Xiaolin
    Zhao, Xinyuan
    JOURNAL OF SEMICONDUCTORS, 2015, 36 (11)
  • [40] Single-Event Upset Responses of Metal-Oxide-Metal Capacitors and Diodes Used in Bulk 65-nm CMOS Analog Circuits
    Xu, Rui
    Hsu, Chen-Kai
    Kalani, Sarthak
    Ban, Jaroslav
    Wang, Qiang
    Ochoa, Ines
    Burton, Charles
    Unal, Mesut
    Sun, Nan
    Kinget, Peter
    Parsons, John
    Andeen, Timothy
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2020, 67 (04) : 698 - 707