Design and implementation of an ASIP for SHA-3 hash algorithm

In recent years, application specific instruction set processor (ASIP) has attracted many researchers attention. These processors resemble application specific integrated circuits (ASICs) and digital signal processors (DSPs) from the performance and flexibility point of view, respectively. In other words, ASIP makes compromise between performance and flexibility criteria. The SHA-3 hashing algorithm has been introduced as the safest and the newest algorithm in 2015 as a global standard. In this paper, a processor with specific instruction set is designed and implemented with regard to variant execution steps of this algorithm. In order to do the modelling and simulation of the processor, we have used the VHDL hardware description language and the ModelSim SE 6.1 tool. Moreover, in order to implement it on a field programmable gate array (FPGA) platform we have used the Xilinx ISE 10.1 tool. The implemented processor has 213.356 MHz operating frequency and 3.004 Mbps throughput.