Heterogenity-aware Scheduling Research on Performance Asymmetric Multicore Processors

被引：0
|
作者：
Zhao S. [1 ,2 ]
Yang Q.-S. [1 ]
Li M.-S. [1 ]
机构：
[1] National Engineering Research Center of Fundamental Software, Institute of Software, Chinese Academy of Sciences, Beijing
[2] University of Chinese Academy of Sciences, Beijing
来源：
Ruan Jian Xue Bao/Journal of Software | 2019年 / 30卷 / 04期
基金：
美国国家科学基金会;
关键词：
AMP; Heterogeneous multi-cores; Heterogeneous scheduling; Scheduling algorithm; Thread assignment;
D O I：
10.13328/j.cnki.jos.005811
中图分类号：
学科分类号：
摘要：
To meet the diverse needs of the applications, heterogeneous multicore processors appeared and entered into market, where the processing cores have a different microarchitecture or instruction set architecture (ISA), providing special features such as instruction level parallelism (ILP) and memory level parallelism (MLP). These cores work together to meet the optimization objectives of the entire computing system, such as high performance, low power consumption or energy efficiency. However, the mainstream scheduling technology is designed for the traditional homogeneous processor architecture, without considering the differences of processing capabilities of various cores. It is worth exploring for scheduling technologies that can perceive the heterogeneous characteristics of the hardware and make more suitable matching decision between applications and hardware resources. The researches of heterogeneous scheduling in recent years are systematically summarized in the paper. This paper also analyzes the scheduling challenges and techniques under the environment of performance asymmetric multicore processors from the following aspects: optimization objectives, analysis model, scheduling decision, and algorithm evaluation. Finally, the future work is prospected from the perspective of software and hardware integration. © Copyright 2019, Institute of Software, the Chinese Academy of Sciences. All rights reserved.
引用
收藏
页码：1164 / 1190
页数：26
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  • [91] Sawalha L., Barnes R.D., Energy-efficient phase-aware scheduling for heterogeneous multicore processors, Proc. of the Green Technologies Conf, pp. 1-6, (2012)
  • [92] Li T., Baumberger D., Koufaty D.A., Et al., Efficient operating system scheduling for performance-asymmetric multi-core architectures, Proc. of the 2007 ACM/IEEE Conf. on Supercomputing, (2007)
  • [93] Muthukaruppan T.S., Pathania A., Mitra T., Price theory based power management for heterogeneous multi-cores, Proc. of the Int'l Conf. on Architectural Support for Programming Languages & Operating Systems, pp. 161-176, (2014)
  • [94] Van Craeynest K., Eeckhout L., Understanding fundamental design choices in single-ISA heterogeneous multicore architectures, ACM Trans. on Architecture and Code Optimization, 9, 4, pp. 1-23, (2013)
  • [95] Mittal S., A survey of techniques for architecting and managing asymmetric multicore processors, ACM Computing Surveys, 48, 3, pp. 1-38, (2016)
  • [96] Shiu E., Prakash S., System challenges and hardware requirements for future consumer devices: From wearable to ChromeBooks and devices in-between, Proc. of the 2015 Symp. on VLSI Technology, pp. 1-5, (2015)
  • [97] Zhou X., Yang J., Xu Y., Et al., Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. on Parallel and Distributed Systems, 21, 1, pp. 60-71, (2010)
  • [98] Xu T.C., Liljeberg P., Plosila J., Et al., Exploration of heuristic scheduling algorithms for 3D multicore processors, Proc. of the Map2MPSoC/SCOPES, pp. 22-31, (2012)
  • [99] Srinivasan S., Iyer R., Zhao L., Et al., HeteroScouts: Hardware assist for OS scheduling in heterogeneous CMPs, Proc. of the ACM SIGMETRICS Joint Int'l Conf. on Measurement & Modeling of Computer Systems, (2011)
  • [100] Vetter J.S., Mittal S., Opportunities for nonvolatile memory systems in extreme-scale high-performance computing, Computing in Science & Engineering, 17, 2, pp. 73-82, (2015)
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