Heterogenity-aware Scheduling Research on Performance Asymmetric Multicore Processors

被引：0
|
作者：
Zhao S. [1 ,2 ]
Yang Q.-S. [1 ]
Li M.-S. [1 ]
机构：
[1] National Engineering Research Center of Fundamental Software, Institute of Software, Chinese Academy of Sciences, Beijing
[2] University of Chinese Academy of Sciences, Beijing
来源：
Ruan Jian Xue Bao/Journal of Software | 2019年 / 30卷 / 04期
基金：
美国国家科学基金会;
关键词：
AMP; Heterogeneous multi-cores; Heterogeneous scheduling; Scheduling algorithm; Thread assignment;
D O I：
10.13328/j.cnki.jos.005811
中图分类号：
学科分类号：
摘要：
To meet the diverse needs of the applications, heterogeneous multicore processors appeared and entered into market, where the processing cores have a different microarchitecture or instruction set architecture (ISA), providing special features such as instruction level parallelism (ILP) and memory level parallelism (MLP). These cores work together to meet the optimization objectives of the entire computing system, such as high performance, low power consumption or energy efficiency. However, the mainstream scheduling technology is designed for the traditional homogeneous processor architecture, without considering the differences of processing capabilities of various cores. It is worth exploring for scheduling technologies that can perceive the heterogeneous characteristics of the hardware and make more suitable matching decision between applications and hardware resources. The researches of heterogeneous scheduling in recent years are systematically summarized in the paper. This paper also analyzes the scheduling challenges and techniques under the environment of performance asymmetric multicore processors from the following aspects: optimization objectives, analysis model, scheduling decision, and algorithm evaluation. Finally, the future work is prospected from the perspective of software and hardware integration. © Copyright 2019, Institute of Software, the Chinese Academy of Sciences. All rights reserved.
引用
收藏
页码：1164 / 1190
页数：26
相关论文
共 100 条
  • [1] Yeric G., Moore's law at 50: Are we planning for retirement, Proc. of the IEEE Int'l Electron Devices Meeting, pp. 1.1.1-1.1.8, (2015)
  • [2] Venkat A., Tullsen D.M., Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor, ACM SIGARCH Computer Architecture News, pp. 121-132, (2014)
  • [3] Pricopi M., Mitra T., Bahurupi: A polymorphic heterogeneous multi-core architecture, ACM Trans. on Architecture and Code Optimization, 8, 4, pp. 1-21, (2012)
  • [4] Greenhalgh P., Big.LITTLE processing with ARM Cortex<sup>TM</sup>-A15 & Cortex-A7, Proc. of the ARM, pp. 1-8, (2011)
  • [5] Becchi M., Crowley P., Dynamic thread assignment on heterogeneous multiprocessor architectures, Proc. of the 3rd Conf. on Computing Frotiers, (2006)
  • [6] Lugini L., Petrucci V., Mosse D., Online thread assignment for heterogeneous multicore systems, Proc. of the 41st Int'l Conf. on Parallel Processing Workshops, pp. 538-544, (2012)
  • [7] Rehman M., Asfand-E-Yar M., Scheduling on heterogeneous multi-core processors using stable matching algorithm, Int'l Journal of Advanced Computer Science and Applications, 7, 6, (2016)
  • [8] Nie P., Duan Z., Efficient and scalable scheduling for performance heterogeneous multicore systems, Journal of Parallel and Distributed Computing, 72, 3, pp. 353-361, (2012)
  • [9] Saez J.C., Prieto M., Fedorova A., Blagodurov S., A Comprehensive Scheduler for Asymmetric Multicore Systems, New York: Association for Computing Machinery, pp. 139-152, (2010)
  • [10] Luo Y.C., Packirisamy V., Hsu W.C., Zhai A., Energy efficient speculative threads: Dynamic thread allocation in same-ISA heterogeneous multicore systems, Proc. of the 19th Int'l Conf. on Parallel Architectures and Compilation Techniques, pp. 453-464, (2010)
12345678910