Design of Universal Code Generator for Multi-Constellation Multi-Frequency GNSS Receiver

被引:0
|
作者
Ba, Xiaohui [1 ,2 ,3 ]
Liu, Taibin [1 ]
Jiang, Wei [1 ,2 ,3 ]
Wang, Jian [1 ,2 ,3 ]
Cai, Baigen [1 ,2 ,3 ]
Chai, Linguo [1 ,2 ,3 ]
Liang, Kun [1 ,2 ,3 ]
机构
[1] Beijing Jiaotong Univ, Sch Automat & Intelligence, Beijing 100044, Peoples R China
[2] Beijing Jiaotong Univ, State Key Lab Rail Transit Control & Safety, Beijing 100044, Peoples R China
[3] Beijing Engn Res Ctr Electromagnet Compatibil & Sa, Beijing 100044, Peoples R China
基金
国家重点研发计划;
关键词
GNSS; IRNSS IZ4; universal code generator; FPGA;
D O I
10.3390/electronics13071244
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A multi-constellation, multi-frequency Global Navigation Satellite System (GNSS) receiver is capable of simultaneously receiving signals from multiple satellite constellations across various frequency bands. This allows for increased observations, thereby enhancing navigation accuracy, continuity, effectiveness, and reliability. The spread spectrum code structures used in satellite navigation signals differ among systems. Compatible code generators are employed in multi-constellation, multi-frequency GNSS receivers to support tasks such as signal acquisition and tracking. There are three main types of spread spectrum code structures: Linear Feedback Shift Register (LFSR), Legendre sequences, and Memory codes. The Indian Regional Navigation Satellite System (IRNSS) released the L1-SPS (Standard Positioning Service) signal format in August 2023, which utilizes the Interleaved Z4-linear ranging code (IZ4 code) as its spread spectrum code. Currently, there is no universal code generator design compatible with the IZ4 code. In this paper, a proposed universal code generator is based on the hardware structure of the IRNSS IZ4 code generator. It achieves compatibility with all LFSR-based spread spectrum codes and enables parallel generation of multiple sets of GNSS signal spread spectrum codes, thereby improving hardware utilization efficiency. The proposed structure is implemented and validated using FPGA design, and resource consumption is provided as part of the validation results.
引用
收藏
页数:14
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