The bifurcation of advanced IC packaging

Following a similar trend from the 1990s, IC package design is experiencing a sea change. As a refresher, this was when ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of BGA. In short, BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. In addition, I/Os were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking, and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like 2.5D/3D-IC and fan-out waferlevel packaging (FOWLP). Instead, in all likelihood, IC design tools and flows will need to be slightly adapted to support the next generation of package designs. This article further examines the design tool/flow requirement for FOWLP, 2.5D/3D-IC, and future multi-die packaging technologies. © 2020 IMAPS-International Microelectronics and Packaging Society. All rights reserved.