Design of 10T SRAM cell with improved read performance and expanded write margin

被引：0
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作者：
Sachdeva, Ashish [1 ]
Tomar, V.K. [1 ]
机构：
[1] ECE Department, GLA University, Mathura,Uttar Pradesh,281406, India
来源：
IET Circuits, Devices and Systems | 2021年 / 15卷 / 01期
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页码：42 / 64
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