Interleaving Clusters of Submodules to Enhance Scalability of Modular Multilevel Converters for High-Voltage Applications

被引:1
|
作者
Na, Jongseo [1 ]
Kim, Heejin [2 ]
Kim, Sangmin [1 ]
Kim, Chan-Ki [3 ]
Mantooth, Homer Alan [4 ]
Hur, Kyeon [1 ]
机构
[1] Yonsei Univ, Sch Elect & Elect Engn, Seoul 03722, South Korea
[2] Pion Elect, R&D Ctr, Yongin 14348, Gyeonggi Do, South Korea
[3] Korea Elect Power Corp KEPCO, Res Inst, Daejeon 34056, South Korea
[4] Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA
基金
新加坡国家研究基金会;
关键词
Voltage control; Capacitors; High-voltage techniques; Harmonic analysis; Decentralized control; Scalability; Synchronization; Flexibility; high-voltage dc (HVDC); modular multilevel converter (MMC); nearest level control (NLC); scalability; DISTRIBUTED CONTROL; PERFORMANCE; FREQUENCY; MMC;
D O I
10.1109/TPWRD.2023.3291403
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article presents a practical architecture for fully exploiting the scalability of modular multilevel converters (MMC) by clustering the submodules (SMs) and interleaving these clusters. The proposed architecture enables scalability and flexibility for various high-voltage applications by dividing the computing tasks of an arm controller among each cluster control iteration, interleaving the output voltages of each cluster to maintain the desired voltage quality without structural changes, and balancing the cluster energy to ensure stable control performance. One noteworthy aspect of the proposed architecture is its implementation of distributed cluster control using a single controller, which eliminates the need for inter-controller synchronization and utilizes hardware resources cost-effectively. The article provides design guidelines for clustering the SMs through theoretical analysis and numerical examples. The validity and performance of the proposed interleaving scheme for the clusters of SMs are demonstrated through hardware-in-the-loop simulation (HILS).
引用
收藏
页码:555 / 564
页数:10
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