Identification Method of Parasitic Components in a Power Loop on PCBs using a VNA Port Extension

被引：0

作者：

Nomura Y. ^{[1
]}

Funaki T. ^{[1
]}

机构：

[1] Department of Electronic and Information Engineering, Osaka University, 2-1, Yamadaoka, Suita, Osaka

来源：

IEEJ Transactions on Industry Applications | 2022年 / 142卷 / 06期

关键词：

high frequency inverter; parasitic components; power loop; vector network analyzer;

D O I：

10.1541/ieejias.142.488

中图分类号：

学科分类号：

摘要：

This paper proposes a measurement method of parasitic components in a PCB for a high-frequency and high-voltage inverter circuit. The proposed method enables accurate measurements by using a VNA port extension and a 50 Ω microstrip line. Parasitic components can be extracted accurately by considering the uncertainty in S parameter measurements. © 2022 The Institute of Electrical Engineers of Japan.

引用

页码：488 / 489

页数：1

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