A REVIEW OF PLANAR TECHNIQUES FOR MULTICHIP MODULES

In VLSI and ULSI integrated circuit IC fabrication, the problem of planarity is well known, particularly at the intermetallic level. Numerous planarization approaches involving either the materials and/or techniques have been put forward. For multichip module (MCM) fabrication, thin film multilayer substrates with excellent characteristics have become increasingly essential for miniaturizing and achieving a high level of functionality. Therefore, as for IC fabrication, topography induced problems increase with increasing integration density. In this paper, we review various planar techniques which can be used in the fabrication of multilevel interconnects and compare their interest for MCM's.