COMBINED HARDWARE SELECTION AND PIPELINING IN HIGH-PERFORMANCE DATA-PATH DESIGN

At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks, and a constraint on the minimal clock frequency. In this paper an algorithm which optimally selects hardware blocks for implementing these abstract building blocks is presented. Furthermore, a technique for hierarchical redistribution and insertion of pipeline registers is presented. Finally, the two optimization tasks are combined. This combination makes the area trade-off between the cost of additional "speedup circuitry" and pipeline registers possible. The developed techniques are based on accurate hierarchical timing models for the hardware blocks. Both hierarchical pipelining and hardware selection are important optimization tasks in the design of high-performance data paths. The automation relieves the designer of the numerous, time-consuming critical path verifications and area evaluations that are required to explore the large design space. The implementation of the algorithms has resulted in a CAD tool called HANDEL, embedded in the data-path compiler CHOPIN.