A VLSI IMPLEMENTATION OF PARALLEL IMAGE-RECONSTRUCTION

For the past few years, computer scientists have studied a new processing model characterized by the execution of operations in parallel. The interest in this model is explained by the great complexity of problems such as signal and image processing, which cannot be solved by the limited sequential model of Von Neumann. We propose a highly parallel architecture based upon a regular network of cells that have the characteristic of being completely asynchronous and able to communicate between themselves using a message routing mechanism. Each cell includes a simple processing part that realizes the necessary functions of the application and a routing part that ensures message transportation. This architecture allows one to process algorithms that are not regular enough to be implemented on SIMD machines. Many applications already studied for this cellular array are logic simulation, neural network, and image reconstruction. Most of the image processing algorithms can be processed by a systolic array of cells, each dealing with one pixel. But image reconstruction algorithms form a new class of problems because the paths the information must follow are not regular. The messages containing reconstruction information move in the network in different directions. Moreover there are message collisions and the cells do not have the same number of messages to process. Message contention is realized in an automatic manner by cell asynchronism. The architecture has been validated by the development of a complete machine dedicated to image reconstruction. For this application, each cell deals with a subimage, and the cellular array is used to realize back-projection and projection processing, which are essential in reconstruction techniques. The different cell parameters are defined according to temporal constraints, such that excellent performance and good global activity of the network are obtained. The interface of such an architecture in a host environment has been studied. An integrated circuit including one cell has been designed for the development of a demonstration machine. In this paper, we describe this highly parallel architecture and explain how it is very efficient in dealing with irregular data. We also present the whole machine for image reconstruction and its performance. © 1991.