A DIGITAL PHASE-LOCKED LOOP FOR GENERATING FREQUENCY DISCRIMINATING DIGITAL WORDS

被引：4
|
作者：
SAHA, AR [1 ]
MAZUMDER, BC [1 ]
机构：
[1] WEBEL RES & DEV CTR,CALCUTTA 700088,INDIA
来源：
PROCEEDINGS OF THE IEEE | 1982年 / 70卷 / 02期
关键词：
D O I：
10.1109/PROC.1982.12265
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：200 / 201
页数：2
相关论文
共 50 条
  • [21] A New Approach on Design of a Digital Phase-Locked Loop
    Ahn, Choon Ki
    Shi, Peng
    You, Sung Hyun
    IEEE SIGNAL PROCESSING LETTERS, 2016, 23 (05) : 600 - 604
  • [22] Intelligent phase-locked loop for digital network synchronization
    Zhang, Qingnan
    Zhao, Xin
    Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University, 1991, 25 (05): : 91 - 98
  • [23] A digital phase-locked loop based LLRF system
    Fu, Xiaoliang
    Fong, Ken
    Yin, Zhiguo
    Zheng, Qiwen
    Au, Thomas
    NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2020, 962
  • [24] NEW DUAL DIGITAL PHASE-LOCKED LOOP.
    Yamasaki, Shoichiro
    Nakagawa, Masao
    Tsunogae, Toshio
    Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 1986, 69 (05): : 67 - 74
  • [25] Fractional-order digital phase-locked loop
    El-Khazali, Reyad
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 963 - 966
  • [26] Modeling and Simulation of Digital Phase-Locked Loop in Simulink
    Parkaban, N.
    Robens, M.
    Grewing, C.
    Christ, V.
    Liebau, D.
    Muralidharan, P.
    Nielinger, D.
    Yegin, U.
    Zambanini, A.
    van Waasen, S.
    15TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2018), 2018, : 121 - 124
  • [27] MULTILOOP HYBRID DIGITAL PHASE-LOCKED LOOP.
    Majumdar, T.
    Bhattacharya, A.K.
    Ray, S.K.
    Biswas, B.N.
    1600, (28):
  • [28] WIDEBAND ALL-DIGITAL PHASE-LOCKED LOOP
    YAMAMOTO, H
    MORI, S
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1975, 58 (03): : 27 - 34
  • [29] NEW INTEGRATED CIRCUIT DIGITAL PHASE-LOCKED LOOP
    LEE, WH
    HARRINGTON, EV
    COX, DB
    IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 1975, 11 (04) : 682 - 682
  • [30] A Digital Phase-locked Loop Based on MAP in PLC
    Wu, Zhilan
    PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION IN COMMUNICATION, 2009, : 76 - 79
12345