An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers

In this paper, an optimum body biasing for gain and linearity control in CMOS Low Noise Amplifier (LNA) is discussed. A digitally controlled highly linear CMOS LNA has been designed and implemented in a 0.13 mu m CMOS process. An off chip Digital to Analog Converter (DAC) is used to generate the proper body bias voltage corresponding to a maximum of the input referred third order intercept point (IIP3). The LNA is suitable for reconfigurable purposes due to its smooth control of gain and linearity. It is dedicated to wireless sensor network applications in the 2.4 GHz ISM Band. The circuit achieves 12.4 dB nominal gain, 4.2 dB noise figure (NF), and -1 dBm IIP3 while drawing 3.1 mA at a 1 V supply. When adjusting the body bias to -0.55 V, the IIP3 peaks at 6 dBm for a 1.7 mA current consumption. The gain and NF are 8.9 dB and 6.2 dB respectively.