共 50 条
- [41] Design of 4-bit reversible shift registers [J]. 1600, World Scientific and Engineering Academy and Society, Ag. Ioannou Theologou 17-23, Zographou, Athens, 15773, Greece (12):
- [42] 4-bit per cell NROM reliability [J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 547 - 550
- [44] Memory Efficient Optimizers with 4-bit States [J]. ADVANCES IN NEURAL INFORMATION PROCESSING SYSTEMS 36 (NEURIPS 2023), 2023,
- [45] Synthesis of the Optimal 4-bit Reversible Circuits [J]. PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 653 - 656
- [46] A JOSEPHSON 4-BIT RALU FOR A PROTOTYPE COMPUTER [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (04) : 1076 - 1084
- [50] APPLYING PRESETTABLE 4-BIT RIPPLE COUNTERS [J]. ELECTRONIC PRODUCTS MAGAZINE, 1971, 14 (07): : 54 - &