Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters

The paper presents design techniques that enable the realization of micro-power algorithmic ADCs with potential applications in implantable biomedical devices and autonomous wireless sensor networks. Digital calibration and switched amplifiers are employed to reduce the analog power requirements. Additionally, the ADC is operated at a low voltage to minimize the digital power dissipation. Clock boosting, dc common mode level shifting, and an inversion coefficient based design methodology facilitate analog operation at low supply voltages. Simulation results indicate that a 10-bit, 50 kS/s converter realized in 0.5-mu m CMOS dissipates 40 mu W operating at a supply of 1.5 V.