METHODOLOGY AND RESULTS OF SYNCHRONOUS DIGITAL HIERARCHY NETWORK PAYLOAD JITTER SIMULATION

Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) network implementations indicate that the jitter on the transported data exceeds desirable values in some situations. Previous researchers have written high level behavioral simulation models to study the sources and the characteristics of this jitter. These behavioral simulation models have fast run times but do not accurately model the jitter sources. The models' sampling rates are too low to capture the frame structure effects which can occur at up to 19.44 MHz. This paper's simulation model takes a more detailed approach than previous behavioral simulations by modelling the network at a bit-by-bit level via event driven simulation. Actual network data is not passed through the computer model. Instead a unique method of transmitting the number of Plesiochronous Digital Hierarchy (PDH) data bits carried in each SDH/SONET byte is used. This work's results include mathematical models for the jitter generation mechanisms as well as numerical values for network jitter.