Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems

Power-efficient digital systems are becoming a pressing requirement for the increasing number of portable and battery operated devices in use today. Power-aware synthesis is therefore becoming a primary target of automated datapath synthesis tools. We take a look at how the retiming transformation can be exploited to generate energy-efficient schedules during behavioral synthesis. Traditionally, retiming is employed on the gate level netlist of a design with the objective of minimizing the critical path delay. For fixed throughput designs, the resultant speedup obtained after retiming the gate-level design can be traded off for a lower supply voltage. We show that the same principle is applicable to the design at a much higher level of abstraction. In particular, we demonstrate how pre-processing a design with retiming can result in more energy-efficient schedules. For standard benchmark examples, this pre-processing scheme can yield energy reduction over 30% using V-dd scaling. A maximum of up to 3.9x energy reduction was achieved for an area penalty of 1.9x using the combined retiming and scheduling approach.