HIGH-PERFORMANCE SUB-0.1 MU-M SILICON N-METAL OXIDE SEMICONDUCTOR TRANSISTORS WITH COMPOSITE METAL POLYSILICON GATES

被引:4
|
作者
RISHTON, SA
MII, YJ
KERN, DP
TAUR, Y
LEE, KY
LII, T
JENKINS, K
QUINLAN, D
BROWN, T
DANNER, D
SEWELL, F
POLCARI, M
机构
来源
关键词
D O I
10.1116/1.586635
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new fabrication process for sub-0.1 mum silicon n-metal-oxide-semiconductor field effect transistors with composite metal/polysilicon gates is described. Gate resistance is reduced below that of plain polysilicon or silicided gates, so that higher speed performance is obtained from shorter gate length devices. The process has resulted in 0.08 mum channel length ring oscillators with record per stage delays of 10.5 ps at 85 K and 13 ps at room temperature, and unity-current-gain cutoff frequencies of 119 GHz at 85 K and 93 GHz at 300 K. Record high transconductances of 1040 mS/mm at 85 K and 740 mS/mm at 300 K have been measured in 0.05 mum channel length devices.
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收藏
页码:2612 / 2614
页数:3
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