CONSISTENCY AND OBSERVABILITY INVARIANCE IN MULTI-LEVEL LOGIC SYNTHESIS

被引：1
|
作者：
MCGEER, P
BRAYTON, RK
机构：
来源：
1989 IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS | 1989年
关键词：
D O I：
10.1109/ICCAD.1989.76984
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：426 / 429
页数：4
相关论文
共 50 条
  • [1] FAST 2-LEVEL LOGIC MINIMIZERS FOR MULTI-LEVEL LOGIC SYNTHESIS
    SAVOJ, H
    MALIK, AA
    BRAYTON, RK
    [J]. 1989 IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1989, : 544 - 547
  • [2] Synthesis of multi-level networks in a programmable logic array
    Cheremismova, LD
    [J]. AUTOMATIC CONTROL AND COMPUTER SCIENCES, 1999, 33 (03) : 57 - 63
  • [3] Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis
    Ben Jamaa, M. Haykel
    Mohanram, Kartik
    De Micheli, Giovanni
    [J]. DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 622 - +
  • [4] Learning Multi-Level Consistency for Noisy Labels
    Tong, Ziye
    Xi, Wei
    [J]. 2022 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2022,
  • [5] Decomposition based approach for synthesis of multi-level threshold logic circuits
    Gowda, Tejaswi
    Vrudhula, Sarma
    [J]. 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 31 - 36
  • [6] Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation
    Neto, Walter L.
    Possani, Vinicius N.
    Marranghello, Felipe S.
    Matos, Jody M.
    Reis, Andre, I
    Ribas, Renato P.
    [J]. 2018 31ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI), 2018,
  • [7] Multi-Level Approximate Logic Synthesis under General Error Constraints
    Miao, Jin
    Gerstlauer, Andreas
    Orshansky, Michael
    [J]. 2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2014, : 504 - 510
  • [8] LOGIC DECOMPOSITION ALGORITHMS FOR THE TIMING OPTIMIZATION OF MULTI-LEVEL LOGIC
    PAULIN, PG
    POIROT, FJ
    [J]. PROCEEDINGS - IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS, 1989, : 329 - 333
  • [9] Multi-level Logic Benchmarks: An Exactness Study
    Amaru, Luca
    Soeken, Mathias
    Haaswijk, Winston
    Testa, Eleonora
    Vuillod, Patrick
    Luo, Jiong
    Gaillardon, Pierre-Emmanuel
    De Micheli, Giovanni
    [J]. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, : 157 - 162
  • [10] Multi-level implementation of delay - Insensitive logic
    Lemberski, I
    Kim, K
    [J]. TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING, 2004, : B187 - B190
12345