REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY

被引：1
|
作者：
WANG, JJ
JEN, CW
机构：
来源：
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | 1990年 / 137卷 / 03期
关键词：
D O I：
10.1049/ip-e.1990.0027
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A systematic design methodology for redundant systolic arrays is proposed. Redundancies consisting of space-shift, time-shift and space - time-shift schemes are applied successfully to detect or mask permanent faults, transient faults or both. Various redundancy designs for different utilisation efficiencies of processor elements can be obtained at the design stage by a dependent graph and its associated algebraic transformation. A customised optimal redundant systolic array design can be achieved for various performance requirements, including throughput rate, latency, average computation time, hardware cost and capabilities of fault detection and fault masking.
引用
收藏
页码：218 / 226
页数：9
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