HIGH-ENERGY ION-IMPLANTATION FOR ELECTRICAL ISOLATION OF MICROELECTRONIC DEVICES

Recent developments in the use of high-energy ion implantation for electrical isolation of both group IV (Si) and III-V (InP, GaAs) devices are presented. For Si devices, dielectric isolation can be achieved with the fabrication of a buried SiO2 layer by high-dose (approximately 10(18)/cm2), high-energy (1 MeV) O-ion implantation. With MeV implant energies, implant temperatures (approximately 150-degrees-C) can be significantly reduced compared to those required (approximately 550-degrees-C) in a conventional, low-energy (150-200 keV) SIMOX fabrication process and consequently, striking differences in post-anneal defect structures are apparent. Also, novel methodologies (high-energy O and Si co-implantation) for achieving low defect density SIMOX material are described. For III-V devices, electrical isolation can be accomplished with the production of implantation-induced disorder wherein the resulting deep-levels effectively trap charge carriers. Conventional, low-energy (100-200 keV) implant isolation schemes necessitate multiple-energy, multiple-ion implant sequences. In the present report, a single, low-dose (approximately 10(13)/cm2), high-energy (5 MeV) 0-ion implant is shown to result in comparable electrical isolation with significant processing simplification.