AN ACCURATE ON-RESISTANCE MODEL FOR LOW-VOLTAGE VDMOS DEVICES

被引：5

作者：

KIM, SD ^{[1
]}

KIM, IJ ^{[1
]}

HAN, MK ^{[1
]}

CHOI, YI ^{[1
]}

机构：

[1] AJOU UNIV,DEPT ELECTR ENGN,SUWON 442749,SOUTH KOREA

来源：

SOLID-STATE ELECTRONICS | 1995年 / 38卷 / 02期

关键词：

D O I：

10.1016/0038-1101(94)00122-V

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An accurate on-resistance model of VDMOS devices in the low voltage regimes is proposed and verified by numerical simulation results. The model considers the lateral Gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping. Results of the proposed model are in good agreement with those of 2D and quasi-3D simulations obtained by PISCES-IIB for a VDMOS device with 100 V rating. The on-resistance of a low voltage VDMOS may be considerably overestimated if it is analyzed by the conventional method.

引用

页码：345 / 350

页数：6

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