A 3-DIMENSIONAL DEVICE SIMULATOR FOR RADIATION-HARD MOS-SOS TRANSISTORS

The effect of the edge parasitic transistor on MOSFET device characteristics fabricated on silicon-on-sapphire (SOS) wafers is analyzed with a new three-dimensional (3D) device simulator. The program performs a numerical solution of the basic semiconductor equations in three dimensions using up-to-date models for the carrier mobilities (including a new field-dependent surface-scattering model) and generation-recombination rates. In addition, depth-dependent models for the carrier mobilities and lifetimes have been introduced to account for the degradation of these parameters near the back interface of SOS films. A novel numerical strategy is implemented that results in efficient and accurate solutions of the floating substrate problem. The accuracy of the simultaneous solution (necessary to solve the floating substrate condition) and the efficiency of Gummel's sequential method are combined to find the two-carrier solution in the full 3D structure. Radiation-induced leakage currents are modeled by adding distributions of charges at the silicon/sapphire interface. The validity of the assumed interface charge distribution model is reinforced by the agreement between simulated and measured post-radiation subthreshold characteristics.