EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL-FILTERS

被引：6

作者：

WANG, CL

WEI, CH

CHEN, SH

机构：

[1] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU,TAIWAN

[2] NATL CHIAO TUNG UNIV,DEPT COMMUN ENGN,HSINCHU,TAIWAN

来源：

IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS | 1988年 / 6卷 / 03期

关键词：

D O I：

10.1109/49.1916

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：484 / 493

页数：10

共 50 条

[1] APPLICATION OF BIT-LEVEL SYSTOLIC ARRAYS TO PIPELINED ARCHITECTURES FOR WAVE DIGITAL-FILTERS
SUMMERFIELD, S
LAWSON, S
[J]. SYSTOLIC ARRAY PROCESSORS, 1989, : 504 - 513
[2] ON THE APPROXIMATION OF FIR BY IIR DIGITAL-FILTERS
BEDNAR, JB
[J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1983, 31 (01): : 28 - 34
[3] Implementation of a bit-level super-systolic FIR filter
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[4] A HIGH-PERFORMANCE BIT-LEVEL SYSTOLIC ARRAY FOR IIR FILTERING
KNOWLES, SC
MCWHIRTER, JG
EVANS, RA
[J]. CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : 553 - 557
[5] A BIT-LEVEL SYSTOLIC ARRAY FOR DIGITAL CONTOUR SMOOTHING
PETKOV, N
[J]. PARALLEL COMPUTING, 1989, 12 (03) : 301 - 313
[6] DESIGN AND IMPLEMENTATION OF EFFICIENT PIPELINED IIR DIGITAL-FILTERS
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WILLSON, AN
[J]. IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1995, 43 (03) : 579 - 590
[7] EFFICIENT SYSTOLIC IMPLEMENTATION OF COMPLEX DIGITAL-FILTERS
RAGHURAMIREDDY, D
UNBEHAUEN, R
[J]. ELECTRONICS LETTERS, 1991, 27 (08) : 666 - 668
[8] VLSI ARRAY PROCESSORS BLOCK IMPLEMENTATION OF IIR DIGITAL-FILTERS
MERTZIOS, VG
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[J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 1988, 7 (01) : 79 - 94
[9] RECONFIGURABLE SYSTOLIC ARRAY IMPLEMENTATION OF QUADRATIC DIGITAL-FILTERS
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[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1986, 33 (08): : 845 - 848
[10] SYSTOLIC IMPLEMENTATION OF DIGITAL-FILTERS
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ELGUIBALY, F
ANTONIOU, A
[J]. MULTIDIMENSIONAL SYSTEMS AND SIGNAL PROCESSING, 1992, 3 (01) : 63 - 78

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