共 50 条
- [42] Layout parasitic limitations in high-speed circuits 2006 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, 2007, : 375 - +
- [43] ESD Protection for High-Speed Receiver Circuits 2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, : 835 - 840
- [44] Prediction of power requirements for high-speed circuits REAL-WORLD APPLICATIONS OF EVOLUTIONARY COMPUTING, PROCEEDINGS, 2000, 1803 : 247 - 254
- [45] Efficient simulation of interconnects in high-speed circuits 2003 HIGH FREQUENCY POSTGRADUATE STUDENT COLLOQUIUM, 2003, : 81 - 84