A COPROCESSOR FOR HIGH-PERFORMANCE MULTIPROCESSOR ADA TASKING

The complex semantics of Ada tasking cause excessive run-time overhead that cannot be avoided even when using the best compiler technology available. It has been demonstrated that special-purpose hardware can reduce the rendezvous latency with 90-99 % depending on the case [Roo89]. All the necessary extra hardware is contained in a single chip coprocessor which easily can be integrated into standard computer hardware. Multiprocessor tasking involves the additional problem of latency and limited bandwidth of the interprocessor communication system. By restructuring the run-time system the communication overhead can be reduced by 90-95 %, which has been demonstrated in a previous project [Lun90]. The success of both these projects has been due to a set of operations or a protocol cleverly tuned to the specific requirements in each case. In the present paper the coprocessor approach will be used and it will be extended to cover also the distributed tasking protocol developed in the previous project.