SINGLE-PRECISION MULTIPLIER WITH REDUCED CIRCUIT COMPLEXITY FOR SIGNAL-PROCESSING APPLICATIONS

被引：67
|
作者：
LIM, YC
机构：
[1] Electrical Engineering Department, National University of Singapore
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1992年 / 41卷 / 10期
关键词：
REDUCED COMPLEXITY MULTIPLIER; SIGNAL PROCESSING VLSI; SINGLE-PRECISION ARITHMETIC;
D O I：
10.1109/12.166611
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
When two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the computation of the least significant part that will ripple into the most significant part of the product. This will produce single-precision multiplier with significantly reduced circuit complexity. In this paper, we present three novel methods for realizing this class of reduced complexity single-precision multipliers. Their performances are also analyzed.
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页码：1333 / 1336
页数：4
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