DESIGN AND CHARACTERIZATION OF A 1 MEGABIT BUBBLE MEMORY DEVICE WITH RELAXED FUNCTION DESIGNS

被引：2

作者：

YANASE, T ^{[1
]}

INOUE, H ^{[1
]}

IWASA, S ^{[1
]}

ORIHARA, S ^{[1
]}

MATSUYAMA, S ^{[1
]}

机构：

[1] FUJITSU LTD,SUZAKA,JAPAN

来源：

JOURNAL OF APPLIED PHYSICS | 1981年 / 52卷 / 03期

关键词：

D O I：

10.1063/1.328946

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

引用

页码：2398 / 2400

页数：3

共 23 条

[1] DESIGN AND FABRICATION OF A 1 MEGABIT BUBBLE MEMORY DEVICE
YANASE, T
INOUE, H
MAJIMA, T
FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1982, 18 (02): : 307 - 342
[2] 8-MU-M PERIOD BUBBLE MEMORY DEVICE WITH RELAXED FUNCTION DESIGNS
ORIHARA, S
YANASE, T
MAJIMA, T
IEEE TRANSACTIONS ON MAGNETICS, 1979, 15 (06) : 1692 - 1696
[3] AN 8-MU-M PERIOD BUBBLE MEMORY DEVICE WITH RELAXED FUNCTION DESIGNS
ORIHARA, S
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1980, 127 (01): : 5 - 5
[4] CHARACTERIZATION OF A FULL MILITARY TEMPERATURE-RANGE ONE MEGABIT BUBBLE MEMORY DEVICE
ARBAUGH, LG
FAIRHOLME, RJ
IEEE TRANSACTIONS ON MAGNETICS, 1986, 22 (05) : 1287 - 1289
[5] RELIABILITY CONSIDERATIONS IN THE DESIGN OF ONE-MEGABIT BUBBLE MEMORY CHIPS
DAVIES, JE
CLOVER, RB
LIEBERMAN, B
ROSE, DK
IEEE TRANSACTIONS ON MAGNETICS, 1980, 16 (05) : 1106 - 1110
[6] TRUE SWAP GATE DESIGN FOR ON CHIP CACHE ORGANIZATION MEGABIT BUBBLE MEMORY
KOHARA, H
TAKAHASHI, K
SUGA, S
FUJIWARA, S
IEEE TRANSACTIONS ON MAGNETICS, 1981, 17 (06) : 3038 - 3040
[7] 1ST ONE-MEGABIT BUBBLE MEMORY IS LAUNCHED
不详
ELECTRONIC PRODUCTS MAGAZINE, 1979, 22 (01): : 111 - &
[8] OPTIMIZED DESIGNS OF A 4 MBIT PERMALLOY BUBBLE MEMORY DEVICE
SEKINO, M
EDA, A
HIROSHIMA, M
NISHIDA, H
IEEE TRANSACTIONS ON MAGNETICS, 1986, 22 (05) : 1299 - 1301
[9] OPTIMIZED DESIGNS OF A 4 MBIT PERMALLOY BUBBLE MEMORY DEVICE.
Sekino, M.
Eda, A.
Hiroshima, M.
Nishida, H.
IEEE Transactions on Magnetics, 1986, MAG-22 (05):
[10] MAGNETIC-BUBBLE MEMORY .1. BUBBLE TECHNOLOGY AND MEMORY DEVICE MANUFACTURE
KOWALCHUK, R
CHEN, WS
MENDEL, TW
WESTERN ELECTRIC ENGINEER, 1979, 23 (02): : 2 - 12

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