TESTABILITY GUIDELINES FOR MULTICHIP MODULES

Because of the advantages that they offer in clock rates, real-estate savings, power dissipation savings, weight etc., multichip modules are rapidly becoming a reality in commercial electronics. Solutions to the problems of handling and testing module components and to the fabrication of the modules themselves have pretty much been solved. However, before MCMs can become a reality, it will be necessary to solve the problems associated with the testing and repairing of modules. This article suggests a set of design guidelines which will minimize the probability of undetectable defects and maximize the probability of diagnosing detectable defects. The guidelines revolve mainly around the IEEE 1149.1-1990 Test Access Port and Boundary-Scan Architecture standard as adopted by the IEEE.