SYSTOLIC ARCHITECTURES FOR THE COMPUTATION OF THE DISCRETE HARTLEY AND THE DISCRETE COSINE TRANSFORMS BASED ON PRIME FACTOR DECOMPOSITION

被引：45
|
作者：
CHAKRABARTI, C
JAJA, J
机构：
[1] UNIV MARYLAND,SYST RES CTR,COLLEGE PK,MD 20742
[2] UNIV MARYLAND,INST ADV COMP STUDIES,DEPT ELECT ENGN,COLLEGE PK,MD 20742
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1990年 / 39卷 / 11期
基金：
美国国家科学基金会;
关键词：
Architecture; bit-serial; discrete cosine transform; discrete Hartley transform (DHT); prime-factor decomposition; systolic; VLSI;
D O I：
10.1109/12.61045
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A’ is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic. © 1990 IEEE
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页码：1359 / 1368
页数：10
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