WAFER-SCALE INTEGRATION - FAULT-TOLERANT PROCEDURE

被引：45

作者：

AUBUSSON, RC ^{[1
]}

CATT, I ^{[1
]}

机构：

[1] CAM LTD,ST ALBANS,HERTFORDSHIRE,ENGLAND

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1978年 / 13卷 / 03期

关键词：

D O I：

10.1109/JSSC.1978.1051050

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：339 / 344

页数：6

共 50 条

[1] CONSTRUCTION OF A FAULT-TOLERANT GRID OF PROCESSORS FOR WAFER-SCALE INTEGRATION
ZORAT, A
[J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 1987, 6 (02) : 175 - 189
[2] FAULT-TOLERANT COMMUNICATIONS FOR WAFER-SCALE INTEGRATION OF A PROCESSOR ARRAY
MOORE, WR
MAHAT, R
[J]. MICROELECTRONICS AND RELIABILITY, 1985, 25 (02): : 291 - 294
[3] Fault-tolerant self-organizing map implemented by wafer-scale integration
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Hachiya, I
Moki, K
Kim, JH
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (02) : 257 - 265
[4] WAFER-SCALE INTEGRATION
CATT, I
[J]. WIRELESS WORLD, 1982, 88 (1554): : 67 - 67
[5] WAFER-SCALE INTEGRATION
DAVIS, B
[J]. IEEE SPECTRUM, 1984, 21 (12) : 16 - 16
[6] WAFER-SCALE INTEGRATION
THORPE, T
[J]. WIRELESS WORLD, 1981, 87 (1548): : 43 - 43
[7] DEFECT-TOLERANT HIERARCHICAL SORTING NETWORKS FOR WAFER-SCALE INTEGRATION
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LIANG, SC
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (09) : 1212 - 1222
[8] A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration
Laflamme-Mayer, Nicolas
Kowarzyk, Gilbert
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Sawan, Mohamad
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 27 (02) : 304 - 315
[9] WAFER-SCALE INTEGRATION - FOREWORD
CHAPMAN, GH
BREWER, JE
TEWKSBURY, SK
[J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1995, 18 (03): : 404 - 405
[10] THE TRIALS OF WAFER-SCALE INTEGRATION
MCDONALD, JF
ROGERS, EH
ROSE, K
STECKL, AJ
[J]. IEEE SPECTRUM, 1984, 21 (10) : 32 - 39

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