Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits

Estimation of Peak Dynamic Power (proportional to the switching activity) of digital circuits early in the design flow is crucial to realize a reliable and power-efficient chip. This paper presents a novel satisfiability based formulation to estimate the Peak Dynamic Power on gate-level as well as Lookup-table-level (targeted for FPGAs) netlists. Experimentation with the ISCAS' 85 gate-level benchmark circuits shows that the best and the average estimates of switching activity computed by the proposed approach are 10% and 5% respectively more than the best reported in the literature. Similarly, for LUT-level netlists of ISCAS' 85 benchmark circuits, the best and the average estimates of switching activity computed by the proposed approach are 69.83% and 50% respectively more than the best reported in the literature. Interestingly, for some of the circuits the SAT solver does provide a global optimal solution. The paper also provides empirical insights into the limitations of Automatic Test Pattern Generation-based approaches for peak dynamic power estimation.