THE 2ND LEVEL TRIGGER OF THE L3 EXPERIMENT .1. THE IMPLEMENTATION

The second level trigger of the L3 experiment performs online background rejection and reduces the first level trigger rate to a value fitting with the third level trigger processing capability. Designed around a set of three bit-slice XOP microprocessors, it can process up to 500 first level triggers per second without significant dead time in the data acquisition. At each LEP beam crossing (45/90 kHz) the complete trigger information (5 kbytes) is memorized in a 1.4 gigabyte bandwidth real dual port memory. The XOP processor builds up the trigger block in less than 400 mu s, and signs the background or physics origin of the current event in less than 3 ms. These very high performances rely essentially on the association of parallelism with high speed ECL technology, provided by dedicated processors fully integrated in Fastbus. Emphasis is given here to the specific hardware developed, to its operation and technical aspects of its installation and integration. The system described here ensures the L3 data taking since the beginning of LEP in July 1989 and the online rejection since 1990.