An Integrated Circuit Design for Pruned Tree-Search Vector Quantization Encoding with an Off-Chip Controller

This paper discusses the design of an encoder for pruned tree-search vector quantization (VQ). This allows near-optimal performance in a mean square error sense while keeping the hardware complexity low. The encoder is partitioned into 1) a slave processor chip that computes the distance and performs minimizations and 2) an off-chip controller that directs the search. Pointer addressing is exploited in the codebook memory to keep the controller hardware simple. Inputs to the slave processor include the source vectors, the codevectors, and external control signals. The slave processor outputs the index of the codevector that best approximates the input in a mean square error sense. The input source and codevectors can have a wordlength of 8 b each. An internal wordlength of 24 b allows a maximum of 256 dimensions. The layout for the slave processor has been generated using a 1.2.mu CMOS library and measures 5.76 x 6.6 mm(2). Critical path simulation with SPICE indicates a maximum clock rate of 40 MHz, which results in a throughput of 80 million multiply-accumulates per second. This implies that real-time processing at MPEG rates can be achieved if the number of levels (N) and the number of children at any node (M) obey the constraint M x N < 32.