共 50 条
- [1] Improvements of SEU Tolerance by Spatial Redundancy in Digital Circuits MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, : 123 - +
- [2] INDIRECT TESTING OF DIGITAL-CORRECTION CIRCUITS IN ANALOG-TO-DIGITAL CONVERTERS WITH REDUNDANCY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (07): : 437 - 445
- [5] The Biological Property of Synthetic Evolved Digital Circuits with ESD Immunity - Redundancy or Degeneracy? Journal of Bionic Engineering, 2013, 10 : 396 - 403
- [7] Design of highly parallel linear digital circuits based on symbol-level redundancy 1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 1996, : 104 - 109
- [8] Automated Design Flow for Applying Triple Modular Redundancy (TMR) in Complex Digital Circuits 2018 IEEE 19TH LATIN-AMERICAN TEST SYMPOSIUM (LATS), 2018,
- [10] Verilog HDL Methodology for Redundancy in Digital Circuits Targeting FPGA Technology For Highly Reliable Applications PROCEEDINGS OF 2010 IEEE INTERNATIONAL CONFERENCE ON AUTOMATION, QUALITY AND TESTING, ROBOTICS (AQTR 2010), VOLS. 1-3, 2010,