HARDWARE IMPLEMENTATION OF NEURAL NETWORKS IN JAPAN

被引:6
|
作者
HIRAI, Y [1 ]
机构
[1] UNIV TSUKUBA,INST INFORMAT SCI & ELECTR,TSUKUBA,IBARAKI 305,JAPAN
关键词
ANALOG VLSI; DIGITAL VLSI; NEURAL NETWORK HARDWARE; OPTOELECTRONIC TECHNOLOGY;
D O I
10.1016/0925-2312(93)90019-Y
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, research activities on hardware implementation of neural networks in Japan are reviewed. In Japan, digital, analog, and optoelectronic technologies have been applied to neural network hardware. Among them, digital approach is the most prevailing. Several types of on-chip BP learning have been implemented in digital hardware, and 2.3 GCUPS (Giga Connection Updates Per Second) learning speed has already been attained. Most of the largest Japanese electronic comPanies have developed this kind of system and have run various neural networks on it. Although the most prevailing approach is digital, intensive researches on analog and optoelectronic approaches are also carried out. For analog approach, 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections Per Second) processing speed for Boltzmann machine with 1 bit digital output have been obtained. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.
引用
收藏
页码:3 / 16
页数:14
相关论文
共 50 条
  • [1] Hardware implementation of RAM neural networks
    Simes, ED
    Uebel, LF
    Augusto, D
    Barone, C
    [J]. PATTERN RECOGNITION LETTERS, 1996, 17 (04) : 421 - 429
  • [2] A reconfigurable approach to hardware implementation of neural networks
    Noory, B
    Groza, V
    [J]. CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY, 2003, : 1861 - 1864
  • [3] A Nonuniform Quantizer for Hardware Implementation of Neural Networks
    Altilio, Rosa
    Rosato, Antonello
    Panella, Massimo
    [J]. 2017 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), 2017,
  • [4] Smart Hardware Implementation of Spiking Neural Networks
    Galan-Prado, Fabio
    Rossello, Josep L.
    [J]. ADVANCES IN COMPUTATIONAL INTELLIGENCE, IWANN 2017, PT I, 2017, 10305 : 560 - 568
  • [5] Efficient Hardware Implementation of Threshold Neural Networks
    Zamanlooy, Babak
    Mirhassani, Mitra
    [J]. 2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2012, : 1 - 4
  • [6] Hardware Implementation of Spiking Neural Networks on FPGA
    Han, Jianhui
    Li, Zhaolin
    Zheng, Weimin
    Zhang, Youhui
    [J]. TSINGHUA SCIENCE AND TECHNOLOGY, 2020, 25 (04) : 479 - 486
  • [7] Logarithmic Multiplier in Hardware Implementation of Neural Networks
    Lotric, Uros
    Bulic, Patricio
    [J]. ADAPTIVE AND NATURAL COMPUTING ALGORITHMS, PT I, 2011, 6593 : 158 - 168
  • [8] HARDWARE IMPLEMENTATION OF STOCHASTIC SPIKING NEURAL NETWORKS
    Rossello, Josep L.
    Canals, Vincent
    Morro, Antoni
    Oliver, Antoni
    [J]. INTERNATIONAL JOURNAL OF NEURAL SYSTEMS, 2012, 22 (04)
  • [9] Hardware Implementation of Spiking Neural Networks on FPGA
    Jianhui Han
    Zhaolin Li
    Weimin Zheng
    Youhui Zhang
    [J]. Tsinghua Science and Technology, 2020, 25 (04) : 479 - 486
  • [10] Fault tolerance in neural networks: neural design and hardware implementation
    Torres-Huitzil, Cesar
    Girau, Bernard
    [J]. 2017 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2017,