EFFICIENT VLSI ARCHITECTURES FOR THE ARITHMETIC FOURIER-TRANSFORM (AFT)

Recently, a new method based on the number-theoretic Mobius inversion formula has been proposed for the computation of the discrete Fourier transform (DFT). The arithmetic Fourier transform (AFT), as this method is known, computes N = 2L + 1 Fourier coefficients (in one dimension) with as few as 3N real multiplications and 1. SN 2 real additions. However, the number count of operations is only one of the factors determining the efficiency of a VLSI implementation. In this paper we propose and analyze the area and time complexity of a VLSI implementation of a number of concurrent architectures for the AFT in both one and two dimensions. A careful comparison of the efficiency of VLSI architectures that compute the DFT ranging from the 2-D direct parallel AFT implementation (with a Thompson A * T2 measure of 0 (N8 log2 N log 2s)) to a new nearly optimal row-column E-network 2-D FFT implementation (with an A * T2 value of 0 (4N4 log3 S)) is attempted. The paper is self-contained with respect to the description of the AFT.