PERFORMANCE MODELING OF THE MR-1 MULTIPROCESSOR USING EXTENDED DETERMINISTIC AND STOCHASTIC PETRI NETS

Clustered shared-memory multiprocessors represent an attractive alternative to single-level bus-based systems. By using knowledge about the privacy of data variables, a compiler can reduce run-time contention for shared resources, such as a global memory, by relocating data to processors' local memory and shared cluster memory. This paper outlines the architecture of the MR-1 Multiprocessor, a clustered, shared-memory multiprocessor architecture. Results of a performance analysis of the architecture using both queueing and non-queueing models are presented. Petri nets have been successfully used to model and evaluate the performance of multiprocessor systems. This has motivated us to model the MR-1 multiprocessor system using extended deterministic and stochastic Petri nets (EDSPN). The aim of this paper is to show that EDSPN can effectively specify the MR-1 multiprocessor, and the performance of this system can be obtained by simulating the Petri net specification. Simulation of the architecture is performed using two independent simulators to reveal the accuracy of these performance expressions. The first is a special-purpose MR-l architectural simulator called mr-1-sim. The second simulator is a general-purpose Petri net simulator called EDSIM. EDSIM uses a unique event scheduling scheme to resolve transition conflicts and streamline the simulator's efficiency. This scheduling scheme and how it efficiently schedules transitions is described Several configurations of the MR-1 architecture have been investigated. The system's bandwidth obtained from the simulation of the EDSPN models of the MR-1 system are then compared to those obtained by previously reported analysis and simulations.