Packet Delay Estimation Algorithm against FIFO Waiting for Asymmetric IEEE 1588 System

Performance in IEEE 1588 synchronization depends on several related factors. Among them, the symmetry of packet delay is the most basic one. But most existing networks could not provide symmetry packet delay between master and slave clocks. From research we found that, FIFO waiting during packet transmitting is one of the main reasons that lead the asymmetry. This paper puts forward a packet delay estimation algorithm to select those "lucky packets" which survived from FIFO waiting, attenuating the FIFO waiting effects on IEEE 1588 synchronization. Verified by some meaningful tests, compared with no optimization, in an asymmetry network, the accuracy of packet delay estimation increases almost 25ns with stability increasing almost 2 order, and the accuracy of IEEE 1588 synchronization increases more than one-times with stability increasing almost four-times.