A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18 mu m CMOS process. A low power mixed-signal LC VCO, a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time. The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations. The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3 mu s.