EFFICIENT AND EFFECTIVE PLACEMENT FOR VERY LARGE CIRCUITS

We present a new approach to simulated annealing and a new hierarchical algorithm for row-based placement which has obtained the best results ever reported for a large set of MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are achieved compared with TimberWolfSC v6.0 [13], [14], [17]. Our new hierarchical annealing-based placement algorithm (TimberWolfSC v7.0) yields chip area reductions up to 21% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. Furthermore, TimberWolfSC v7.0 produces lower total wire length by an average of 8% than Gordian/Domino [2], [3], [8], [12], 11% lower wire length than Ritual/Tiger [15], while using comparable run time. TimberWolfSC v7.0 also supports precise timing driven placement [16].