ULTRA-HIGH-SPEED CMOS DESIGN

Circuit and design techniques for high speed logic using standard CMOS processing have been developed. Several experimental chips performing real functions at speeds up to 1 GHz are demonstrated. Beyond normal speed improvement methods, two new methods were used. These were a new clocking technique, the true single phase clock, and transistor sizing using a new optimizer tool, SLOP. The robustness of these techniques has been investigated. Extensions of these methods, to high complexity as well as to much higher speeds, are discussed.