共 50 条
- [2] A design methodology for self-timed event logic pipelines [J]. ESA'04 & VLSI'04, PROCEEDINGS, 2004, : 475 - 479
- [3] SELF - A SELF-TIMED SYSTEMS-DESIGN TECHNIQUE [J]. ELECTRONICS LETTERS, 1987, 23 (06) : 269 - 270
- [4] Self-timed mesochronous interconnection for high-speed VLSI systems [J]. SIXTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1996, : 122 - 125
- [6] Current Sensing Methodology for Completion Detection in Self-timed Systems [J]. 2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), 2011, : 405 - 406
- [7] Characterization Technique to Implement Self-Timed Cells for VLSI Design Blocks. [J]. 2014 11TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTING SCIENCE AND AUTOMATIC CONTROL (CCE), 2014,
- [8] A self-timed Cyclic Redundancy Check (CRC) in VLSI [J]. 40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 1021 - 1025
- [9] DESIGN OF SELF-TIMED MULTIPLIERS - A COMPARISON [J]. ASYNCHRONOUS DESIGN METHODOLOGIES, 1993, 28 : 165 - 179
- [10] Set of self-timed latches for high-speed VLSI [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (06): : 341 - 344