Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings

被引:1
|
作者
Jian, Jie [1 ]
Lai, Mingche [1 ]
Xiao, Liquan [1 ]
机构
[1] Natl Univ Def Technol, Coll Comp, Changsha, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
All Open Access; Gold; Green;
D O I
10.1155/2018/8074074
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
The demand from exascale computing has made the design of high-radix switch chips an attractive and challenging research field in EHPC (exascale high-performance computing). The static power, due to the thermal sensitivity and process variation of the microresonator rings, and the cross talk noise of the optical network become the main bottlenecks of the network's scalability. This paper proposes the analyze model of the trimming power, process variation power, and signal-to-noise ratio (SNR) for the Graphein-based high-radix optical switch networks and uses the extra channels and the redundant rings to decrease the trimming power and the process variation power. The paper also explores the SNR under different configurations. The simulation result shows that when using 8 extra channels in the 64 x 64 crossbar optical network, the trimming power reduces almost 80% and the process variation power decreases 65% by adding 16 redundant rings in the 64 x 64 crossbar optical network. All of these schemes have little influence on the SNR. Meanwhile, the greater channel spacing has great advantages to decrease the static power and increase the SNR of the optical network.
引用
收藏
页数:8
相关论文
共 3 条
  • [1] Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration
    Jian, Jie
    Lai, Mingche
    Xiao, Liquan
    Xu, Weixia
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2016, 2016, 10048 : 162 - 177
  • [2] Hi-Rise: A High-Radix Switch for 3D Integration with Single-cycle Arbitration
    Jeloka, Supreet
    Das, Reetuparna
    Dreslinski, Ronald G.
    Mudge, Trevor
    Blaauw, David
    2014 47TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2014, : 471 - 483
  • [3] 3D Implemented SRAM/DRAM Hybrid Cache Architecture for High-Performance and Low Power Consumption
    Inoue, Koji
    Hashiguchi, Shinya
    Ueno, Shinya
    Fukumoto, Naoto
    Murakami, Kazuaki
    2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,