ANALYSIS OF THE HOLDING CURRENT IN CMOS LATCH-UP

被引：1
|
作者：
MATINO, H
机构：
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 1985年 / 29卷 / 06期
关键词：
SEMICONDUCTOR DEVICES; MOS;
D O I：
10.1147/rd.296.0588
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The holding current in CMOS latch-up with or without well and/or substrate bias has been examined. Measurements indicate that the holding current increases significantly with reverse bias and low shunting base resistance. It is shown that a previous equation for the holding current is inaccurate, and a new equation for holding current with bias is presented.
引用
收藏
页码：588 / 592
页数：5
相关论文
共 50 条
  • [1] ANALYSIS OF LATCH-UP HOLDING VOLTAGE FOR SHALLOW TRENCH CMOS
    GUPTA, RK
    SAKAI, I
    HU, C
    ELECTRONICS LETTERS, 1986, 22 (23) : 1261 - 1263
  • [2] A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
    Chen, MJ
    Lee, HS
    Chen, JH
    Hou, CS
    Lin, CS
    Jou, YN
    IEEE ELECTRON DEVICE LETTERS, 1998, 19 (08) : 276 - 278
  • [3] A compact model of holding voltage for latch-up in epitaxial CMOS
    Chen, MJ
    Hou, CS
    Tseng, PN
    Shiue, RY
    Lee, HS
    Chen, JH
    Jeng, JK
    Jou, YN
    1997 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 35TH ANNUAL, 1997, : 339 - 345
  • [4] ANALYSIS OF LATCH-UP IN CMOS IC
    KYOMASU, M
    ARAKI, T
    OHTSUKI, T
    NAKAYAMA, M
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1978, 61 (02): : 105 - 113
  • [5] AN ANALYTIC MODEL OF HOLDING VOLTAGE FOR LATCH-UP IN EPITAXIAL CMOS
    SEITCHIK, JA
    CHATTERJEE, A
    YANG, P
    IEEE ELECTRON DEVICE LETTERS, 1987, 8 (04) : 157 - 159
  • [6] 3-DIMENSIONAL DISTRIBUTION OF CMOS LATCH-UP CURRENT
    SANGIORGI, E
    RICCO, B
    SELMI, L
    IEEE ELECTRON DEVICE LETTERS, 1987, 8 (04) : 154 - 156
  • [7] A NEW MODEL FOR CMOS LATCH-UP
    WEI, L
    ELNOKALI, M
    SOLID-STATE ELECTRONICS, 1987, 30 (08) : 885 - 887
  • [8] LATCH-UP IN CMOS CIRCUITS - A REVIEW
    SANGIORGI, E
    FIEGNA, C
    MENOZZI, R
    SELMI, L
    RICCO, B
    EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS, 1990, 1 (03): : 337 - 349
  • [9] LATCH-UP ON CMOS EPI DEVICES
    CHAPUIS, T
    CONSTANS, H
    ROSIER, LH
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1990, 37 (06) : 1839 - 1842
  • [10] A BETTER UNDERSTANDING OF CMOS LATCH-UP
    HU, GJ
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (01) : 62 - 67
12345