HARMONIC REDUCTION IN SINGLE-PHASE INVERTERS USING A PARALLEL OPERATION TECHNIQUE

A new technique for harmonic reduction in single-phase inverters, using sinusoidal pulse-width modulation (PWM), is presented. A modified circuit based on parallel operation techniques of MOS inverter sets using interphase reactors as current balancers and reference wave shifting as the modulation strategy is investigated as a means of economically and efficiently reducing the harmonic content of the output waveform. A dedicated signal generator is designed and built to implement this PWM strategy. Good agreement between analytical results and experimental results was observed throughout the project. Detailed analysis shows that harmonics lower than the 15th (or the 29th) are all less than one percent of the fundamental component when the frequency ratio is relatively low (9 or 15). When the frequency ratio is increased to 45, at low output frequency, harmonics lower than the 87th are cancelled from the output waveform. This is done without noticeable reduction in the fundamental component. The results show the feasibility of obtaining practically sinusoidal output waveforms. © 1990 Taylor & Francis Ltd.