A SCALABLE, REAL-TIME, IMAGE-PROCESSING PIPELINE

被引：4
|
作者：
JONKER, PP
KOMEN, ER
KRAAIJVELD, MA
机构：
[1] Pattern Recognition Section, Faculty of Applied Physics, Delft University of Technology, GA Delft, NL-2600
来源：
MACHINE VISION AND APPLICATIONS | 1995年 / 8卷 / 02期
关键词：
REAL-TIME IMAGE PROCESSING; LOW-LEVEL IMAGE PROCESSING; CELLULAR LOGIC PROCESSING; MATHEMATICAL MORPHOLOGY; SYSTOLIC PIPELINE;
D O I：
10.1007/BF01213476
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
To speed up image processing in the field of robot vision and industrial inspection, a pipeline element that can perform fast cellular logic operations was made. This cellular logic processing element (CLPE) can process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI device. It includes a writable logic array for storing sets of 3 x 3 structuring elements that define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed gray-value processing and cellular logic processing.
引用
收藏
页码：110 / 121
页数：12
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