ON MINIMIZING MEMORY IN SYSTOLIC ARRAYS FOR THE DYNAMIC TIME WARPING ALGORITHM

被引：0
|
作者：
DIJKSTRA, E [1 ]
PIGUET, C [1 ]
机构：
[1] CTR SUISSE ELECTR & MICROTECHN SA,CH-2000 NEUCHATEL,SWITZERLAND
来源：
INTEGRATION-THE VLSI JOURNAL | 1986年 / 4卷 / 02期
关键词：
COMPUTER ARCHITECTURE - INFORMATION THEORY - Data compression - INTEGRATED CIRCUITS; VLSI - MATHEMATICAL PROGRAMMING; DYNAMIC;
D O I：
10.1016/S0167-9260(86)80005-0
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
New systolic architectures have been evaluated for the Dynamic Time Warping (DTW) algorithm. This algorithm is a non-linear pattern matching technique used in isolated and continuous speech recognition systems. The proposed systolic decomposition for the DTW algorithm combines simultaneously (1) simple and regular systolic communication schemes (2) a decomposition strategy which aims at a minimum amount of memory. This approach has led to a systolic architecture which is relatively flexible, compact and easy to test.
引用
收藏
页码：155 / 173
页数：19
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