Design and implementation of an ultra-low power passive UHF RFID tag

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 mu m CMOS process with a die size of 800 x 800 mu m(2). Measurement results show that the total power consumption of the tag chip is only 7.4 mu W with a sensitivity of -12 dBm.